RTD-CMOS pipelined networks for reduced power consumption
The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced component count, and/or lower power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS)...
| Autores: | , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión aceptada para publicación |
| Fecha de publicación: | 2011 |
| País: | España |
| Institución: | Universidad de Sevilla (US) |
| Repositorio: | idUS. Depósito de Investigación de la Universidad de Sevilla |
| OAI Identifier: | oai:idus.us.es:11441/76623 |
| Acceso en línea: | https://hdl.handle.net/11441/76623 https://doi.org/10.1109/TNANO.2011.2157518 |
| Access Level: | acceso abierto |
| Palabra clave: | Resonant tunneling diode Nano-pipeline Emerging technologies Logic circuits Power efficiency |
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RTD-CMOS pipelined networks for reduced power consumptionNúñez Martínez, JuanAvedillo de Juan, María JoséQuintana Toledo, José MaríaResonant tunneling diodeNano-pipelineEmerging technologiesLogic circuitsPower efficiencyThe incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced component count, and/or lower power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some studies have concentrated on evaluating the advantages of this incorporation, more work in this direction is required. In this letter, we compare RTD-CMOS and pure CMOS realizations of a logic gate network which can be operated in a gate-level pipeline. Significantly lower average power is obtained for RTD-CMOS implementations.Gobierno de España TEC2007-67245, TEC2010-18937Junta de Andalucía TIC-2961Institute of Electrical and Electronics EngineersElectrónica y ElectromagnetismoGobierno de EspañaJunta de Andalucía2011info:eu-repo/semantics/articleinfo:eu-repo/semantics/acceptedVersionapplication/pdfapplication/pdfhttps://hdl.handle.net/11441/76623https://doi.org/10.1109/TNANO.2011.2157518reponame:idUS. Depósito de Investigación de la Universidad de Sevillainstname:Universidad de Sevilla (US)InglésIEEE Transactions on Nanotechnology, 10 (6), 1217-1220.TEC2007-67245TEC2010-18937TIC-2961http://dx.doi.org/10.1109/TNANO.2011.2157518info:eu-repo/semantics/openAccessoai:idus.us.es:11441/766232026-06-17T12:51:07Z |
| dc.title.none.fl_str_mv |
RTD-CMOS pipelined networks for reduced power consumption |
| title |
RTD-CMOS pipelined networks for reduced power consumption |
| spellingShingle |
RTD-CMOS pipelined networks for reduced power consumption Núñez Martínez, Juan Resonant tunneling diode Nano-pipeline Emerging technologies Logic circuits Power efficiency |
| title_short |
RTD-CMOS pipelined networks for reduced power consumption |
| title_full |
RTD-CMOS pipelined networks for reduced power consumption |
| title_fullStr |
RTD-CMOS pipelined networks for reduced power consumption |
| title_full_unstemmed |
RTD-CMOS pipelined networks for reduced power consumption |
| title_sort |
RTD-CMOS pipelined networks for reduced power consumption |
| dc.creator.none.fl_str_mv |
Núñez Martínez, Juan Avedillo de Juan, María José Quintana Toledo, José María |
| author |
Núñez Martínez, Juan |
| author_facet |
Núñez Martínez, Juan Avedillo de Juan, María José Quintana Toledo, José María |
| author_role |
author |
| author2 |
Avedillo de Juan, María José Quintana Toledo, José María |
| author2_role |
author author |
| dc.contributor.none.fl_str_mv |
Electrónica y Electromagnetismo Gobierno de España Junta de Andalucía |
| dc.subject.none.fl_str_mv |
Resonant tunneling diode Nano-pipeline Emerging technologies Logic circuits Power efficiency |
| topic |
Resonant tunneling diode Nano-pipeline Emerging technologies Logic circuits Power efficiency |
| description |
The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance, producing higher circuit speed, reduced component count, and/or lower power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some studies have concentrated on evaluating the advantages of this incorporation, more work in this direction is required. In this letter, we compare RTD-CMOS and pure CMOS realizations of a logic gate network which can be operated in a gate-level pipeline. Significantly lower average power is obtained for RTD-CMOS implementations. |
| publishDate |
2011 |
| dc.date.none.fl_str_mv |
2011 |
| dc.type.none.fl_str_mv |
info:eu-repo/semantics/article info:eu-repo/semantics/acceptedVersion |
| format |
article |
| status_str |
acceptedVersion |
| dc.identifier.none.fl_str_mv |
https://hdl.handle.net/11441/76623 https://doi.org/10.1109/TNANO.2011.2157518 |
| url |
https://hdl.handle.net/11441/76623 https://doi.org/10.1109/TNANO.2011.2157518 |
| dc.language.none.fl_str_mv |
Inglés |
| language_invalid_str_mv |
Inglés |
| dc.relation.none.fl_str_mv |
IEEE Transactions on Nanotechnology, 10 (6), 1217-1220. TEC2007-67245 TEC2010-18937 TIC-2961 http://dx.doi.org/10.1109/TNANO.2011.2157518 |
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info:eu-repo/semantics/openAccess |
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openAccess |
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application/pdf application/pdf |
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Institute of Electrical and Electronics Engineers |
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Institute of Electrical and Electronics Engineers |
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reponame:idUS. Depósito de Investigación de la Universidad de Sevilla instname:Universidad de Sevilla (US) |
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Universidad de Sevilla (US) |
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idUS. Depósito de Investigación de la Universidad de Sevilla |
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idUS. Depósito de Investigación de la Universidad de Sevilla |
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15,228081 |