Improving robustness of dynamic logic based pipelines

Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in addition to the functional limitation associated to the noninverting behavior of Domino gates, there are also robustness disadvantages when compared to inverting dynamic gates. We an...

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Bibliographic Details
Authors: Quintero, Héctor, Avedillo, María J., Núñez, Juan
Format: article
Status:Versión aceptada para publicación
Publication Date:2016
Country:España
Institution:Consejo Superior de Investigaciones Científicas (CSIC)
Repository:DIGITAL.CSIC. Repositorio Institucional del CSIC
OAI Identifier:oai:dnet:digitalcsic_::c1f4f14f132db5ab003cfbd75787c0e1
Online Access:http://hdl.handle.net/10261/155900
Access Level:Open access
Keyword:Nanopipeline
Dynamic logic
Robust design techniques
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spelling Improving robustness of dynamic logic based pipelinesQuintero, HéctorAvedillo, María J.Núñez, JuanNanopipelineDynamic logicRobust design techniquesDomino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in addition to the functional limitation associated to the noninverting behavior of Domino gates, there are also robustness disadvantages when compared to inverting dynamic gates. We analyze and compare the tolerance to parameter and operating conditions variations of gate-level pipelines implemented with Domino and with DOE, an inverting dynamic gate we have recently proposed. Our experiments confirm that DOE pipelines are more robust and that improvements are due to its noninverting feature.Peer reviewedInstitute of Electrical and Electronics EngineersConsejo Superior de Investigaciones Científicas [https://ror.org/02gfc7t72]201720172016info:eu-repo/semantics/articlehttp://purl.org/coar/resource_type/c_6501Postprintinfo:eu-repo/semantics/acceptedVersionhttp://hdl.handle.net/10261/155900reponame:DIGITAL.CSIC. Repositorio Institucional del CSICinstname:Consejo Superior de Investigaciones Científicas (CSIC)Ingléshttps://doi.org/10.1109/DCIS.2015.7388597Síinfo:eu-repo/semantics/openAccessoai:dnet:digitalcsic_::c1f4f14f132db5ab003cfbd75787c0e12026-05-22T06:33:51Z
dc.title.none.fl_str_mv Improving robustness of dynamic logic based pipelines
title Improving robustness of dynamic logic based pipelines
spellingShingle Improving robustness of dynamic logic based pipelines
Quintero, Héctor
Nanopipeline
Dynamic logic
Robust design techniques
title_short Improving robustness of dynamic logic based pipelines
title_full Improving robustness of dynamic logic based pipelines
title_fullStr Improving robustness of dynamic logic based pipelines
title_full_unstemmed Improving robustness of dynamic logic based pipelines
title_sort Improving robustness of dynamic logic based pipelines
dc.creator.none.fl_str_mv Quintero, Héctor
Avedillo, María J.
Núñez, Juan
author Quintero, Héctor
author_facet Quintero, Héctor
Avedillo, María J.
Núñez, Juan
author_role author
author2 Avedillo, María J.
Núñez, Juan
author2_role author
author
dc.contributor.none.fl_str_mv Consejo Superior de Investigaciones Científicas [https://ror.org/02gfc7t72]
dc.subject.none.fl_str_mv Nanopipeline
Dynamic logic
Robust design techniques
topic Nanopipeline
Dynamic logic
Robust design techniques
description Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in addition to the functional limitation associated to the noninverting behavior of Domino gates, there are also robustness disadvantages when compared to inverting dynamic gates. We analyze and compare the tolerance to parameter and operating conditions variations of gate-level pipelines implemented with Domino and with DOE, an inverting dynamic gate we have recently proposed. Our experiments confirm that DOE pipelines are more robust and that improvements are due to its noninverting feature.
publishDate 2016
dc.date.none.fl_str_mv 2016
2017
2017
dc.type.none.fl_str_mv info:eu-repo/semantics/article
http://purl.org/coar/resource_type/c_6501
Postprint
info:eu-repo/semantics/acceptedVersion
format article
status_str acceptedVersion
dc.identifier.none.fl_str_mv http://hdl.handle.net/10261/155900
url http://hdl.handle.net/10261/155900
dc.language.none.fl_str_mv Inglés
language_invalid_str_mv Inglés
dc.relation.none.fl_str_mv https://doi.org/10.1109/DCIS.2015.7388597
Sí
dc.rights.none.fl_str_mv info:eu-repo/semantics/openAccess
eu_rights_str_mv openAccess
dc.publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
publisher.none.fl_str_mv Institute of Electrical and Electronics Engineers
dc.source.none.fl_str_mv reponame:DIGITAL.CSIC. Repositorio Institucional del CSIC
instname:Consejo Superior de Investigaciones Científicas (CSIC)
instname_str Consejo Superior de Investigaciones Científicas (CSIC)
reponame_str DIGITAL.CSIC. Repositorio Institucional del CSIC
collection DIGITAL.CSIC. Repositorio Institucional del CSIC
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15,228081

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