Multi-unit serial polynomial multiplier to accelerate NTRU-based cryptographic schemes in IoT embedded systems
This article belongs to the Special Issue Advances in Cybersecurity for the Internet of Things.
| Autores: | , , , |
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| Tipo de recurso: | artículo |
| Estado: | Versión publicada |
| Fecha de publicación: | 2022 |
| País: | España |
| Institución: | Consejo Superior de Investigaciones Científicas (CSIC) |
| Repositorio: | DIGITAL.CSIC. Repositorio Institucional del CSIC |
| OAI Identifier: | oai:digital.csic.es:10261/336933 |
| Acceso en línea: | http://hdl.handle.net/10261/336933 |
| Access Level: | acceso abierto |
| Palabra clave: | IoT embedded systems Programmable systems-on-chip Hardware security Postquantum cryptography HW/SW codesign techniques Public-key encryption scheme |
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Multi-unit serial polynomial multiplier to accelerate NTRU-based cryptographic schemes in IoT embedded systemsSánchez-Solano, SantiagoCamacho-Ruiz, ErosMartínez-Rodríguez, Macarena CristinaBrox, PiedadIoT embedded systemsProgrammable systems-on-chipHardware securityPostquantum cryptographyHW/SW codesign techniquesPublic-key encryption schemeThis article belongs to the Special Issue Advances in Cybersecurity for the Internet of Things.Concern for the security of embedded systems that implement IoT devices has become a crucial issue, as these devices today support an increasing number of applications and services that store and exchange information whose integrity, privacy, and authenticity must be adequately guaranteed. Modern lattice-based cryptographic schemes have proven to be a good alternative, both to face the security threats that arise as a consequence of the development of quantum computing and to allow efficient implementations of cryptographic primitives in resource-limited embedded systems, such as those used in consumer and industrial applications of the IoT. This article describes the hardware implementation of parameterized multi-unit serial polynomial multipliers to speed up time-consuming operations in NTRU-based cryptographic schemes. The flexibility in selecting the design parameters and the interconnection protocol with a general-purpose processor allow them to be applied both to the standardized variants of NTRU and to the new proposals that are being considered in the post-quantum contest currently held by the National Institute of Standards and Technology, as well as to obtain an adequate cost/performance/security-level trade-off for a target application. The designs are provided as AXI4 bus-compliant intellectual property modules that can be easily incorporated into embedded systems developed with the Vivado design tools. The work provides an extensive set of implementation and characterization results in devices of the Xilinx Zynq-7000 and Zynq UltraScale+ families for the different sets of parameters defined in the NTRUEncrypt standard. It also includes details of their plug and play inclusion as hardware accelerators in the C implementation of this public-key encryption scheme codified in the LibNTRU library, showing that acceleration factors of up to 3.1 are achieved when compared to pure software implementations running on the processing systems included in the programmable devices.This research was supported in part by the SPIRS Project with Grant Agreement No. 952622 under the EU H2020 research and innovation programme and the ARES Project PID2020-116664RB-100 funded by MCIN/AEI/10.13039/501100011033 and the NextGenerationEU/PRTR. M.C.M.R. holds a Postdoc fellowship from the Andalusia Government with support from PO FSE of EU. E.C.R. is supported by the FPU20/03008 predoc grant from the Spanish government.Peer reviewedMultidisciplinary Digital Publishing InstituteEuropean CommissionAgencia Estatal de Investigación (España)Ministerio de Ciencia, Innovación y Universidades (España)Junta de AndalucíaConsejo Superior de Investigaciones Científicas [https://ror.org/02gfc7t72]202320232022info:eu-repo/semantics/articlehttp://purl.org/coar/resource_type/c_6501Publisher's versioninfo:eu-repo/semantics/publishedVersionapplication/pdfhttp://hdl.handle.net/10261/336933reponame:DIGITAL.CSIC. Repositorio Institucional del CSICinstname:Consejo Superior de Investigaciones Científicas (CSIC)Inglés#PLACEHOLDER_PARENT_METADATA_VALUE##PLACEHOLDER_PARENT_METADATA_VALUE#info:eu-repo/grantAgreement/EC/H2020/952622info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2020-116664RB-I00https://doi.org/10.3390/s22052057Síinfo:eu-repo/semantics/openAccessoai:digital.csic.es:10261/3369332026-05-22T06:33:51Z |
| dc.title.none.fl_str_mv |
Multi-unit serial polynomial multiplier to accelerate NTRU-based cryptographic schemes in IoT embedded systems |
| title |
Multi-unit serial polynomial multiplier to accelerate NTRU-based cryptographic schemes in IoT embedded systems |
| spellingShingle |
Multi-unit serial polynomial multiplier to accelerate NTRU-based cryptographic schemes in IoT embedded systems Sánchez-Solano, Santiago IoT embedded systems Programmable systems-on-chip Hardware security Postquantum cryptography HW/SW codesign techniques Public-key encryption scheme |
| title_short |
Multi-unit serial polynomial multiplier to accelerate NTRU-based cryptographic schemes in IoT embedded systems |
| title_full |
Multi-unit serial polynomial multiplier to accelerate NTRU-based cryptographic schemes in IoT embedded systems |
| title_fullStr |
Multi-unit serial polynomial multiplier to accelerate NTRU-based cryptographic schemes in IoT embedded systems |
| title_full_unstemmed |
Multi-unit serial polynomial multiplier to accelerate NTRU-based cryptographic schemes in IoT embedded systems |
| title_sort |
Multi-unit serial polynomial multiplier to accelerate NTRU-based cryptographic schemes in IoT embedded systems |
| dc.creator.none.fl_str_mv |
Sánchez-Solano, Santiago Camacho-Ruiz, Eros Martínez-Rodríguez, Macarena Cristina Brox, Piedad |
| author |
Sánchez-Solano, Santiago |
| author_facet |
Sánchez-Solano, Santiago Camacho-Ruiz, Eros Martínez-Rodríguez, Macarena Cristina Brox, Piedad |
| author_role |
author |
| author2 |
Camacho-Ruiz, Eros Martínez-Rodríguez, Macarena Cristina Brox, Piedad |
| author2_role |
author author author |
| dc.contributor.none.fl_str_mv |
European Commission Agencia Estatal de Investigación (España) Ministerio de Ciencia, Innovación y Universidades (España) Junta de Andalucía Consejo Superior de Investigaciones Científicas [https://ror.org/02gfc7t72] |
| dc.subject.none.fl_str_mv |
IoT embedded systems Programmable systems-on-chip Hardware security Postquantum cryptography HW/SW codesign techniques Public-key encryption scheme |
| topic |
IoT embedded systems Programmable systems-on-chip Hardware security Postquantum cryptography HW/SW codesign techniques Public-key encryption scheme |
| description |
This article belongs to the Special Issue Advances in Cybersecurity for the Internet of Things. |
| publishDate |
2022 |
| dc.date.none.fl_str_mv |
2022 2023 2023 |
| dc.type.none.fl_str_mv |
info:eu-repo/semantics/article http://purl.org/coar/resource_type/c_6501 Publisher's version info:eu-repo/semantics/publishedVersion |
| format |
article |
| status_str |
publishedVersion |
| dc.identifier.none.fl_str_mv |
http://hdl.handle.net/10261/336933 |
| url |
http://hdl.handle.net/10261/336933 |
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Inglés |
| language_invalid_str_mv |
Inglés |
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#PLACEHOLDER_PARENT_METADATA_VALUE# #PLACEHOLDER_PARENT_METADATA_VALUE# info:eu-repo/grantAgreement/EC/H2020/952622 info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2020-116664RB-I00 https://doi.org/10.3390/s22052057 Sí |
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info:eu-repo/semantics/openAccess |
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openAccess |
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application/pdf |
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Multidisciplinary Digital Publishing Institute |
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Multidisciplinary Digital Publishing Institute |
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reponame:DIGITAL.CSIC. Repositorio Institucional del CSIC instname:Consejo Superior de Investigaciones Científicas (CSIC) |
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Consejo Superior de Investigaciones Científicas (CSIC) |
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DIGITAL.CSIC. Repositorio Institucional del CSIC |
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DIGITAL.CSIC. Repositorio Institucional del CSIC |
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