Database-driven FPGA Workflow for digital system verification
In today's rapidly evolving landscape of digital systems, where complexity is ever-increasing, the verification of these systems stands as a cornerstone of paramount importance. Addressing this critical need, this master thesis introduces a Database-driven FPGA Workflow for digital system verif...
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| Format: | master thesis |
| Publication Date: | 2024 |
| Country: | España |
| Institution: | Universitat Politècnica de Catalunya (UPC) |
| Repository: | UPCommons. Portal del coneixement obert de la UPC |
| Language: | English |
| OAI Identifier: | oai:upcommons.upc.edu:2117/415257 |
| Online Access: | https://hdl.handle.net/2117/415257 |
| Access Level: | Open access |
| Keyword: | Field programmable gate arrays Computer software -- Verification Digital system verification Field-Programmable Gate Array (FPGA) Register-Transfer Level (RTL) Matrius de portes programables per l'usuari Programari--Verificació Àrees temàtiques de la UPC::Informàtica::Sistemes d'informació |
| Summary: | In today's rapidly evolving landscape of digital systems, where complexity is ever-increasing, the verification of these systems stands as a cornerstone of paramount importance. Addressing this critical need, this master thesis introduces a Database-driven FPGA Workflow for digital system verification, that seamlessly integrates database management with FPGA programming, transcending vendor-specific constraints to enhance the precision and efficiency of the verification process. The thesis outlines the development of a workflow, tailored to interface seamlessly with a vendor-independent database repository. This repository houses test verification results, forming a platform for verification. This strategy is architected to streamline verification procedures, mitigate potential errors, and establish a methodical framework for managing verification data across diverse FPGA platforms. The methodology, comprises a sequence of steps executed by a Rust program. Beginning with the extraction of RTL code from a Git repository, the Rust program automates synthesis, implementation, and generation of bitstream using tools such as AMD Xilinx Vivado or equivalents from other FPGA vendors. It then verifies the output against a reference file and stores the verification data in a database. |
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