A versatile CMOS transistor array IC for the statistical characterization of time-zero variability, RTN, BTI, and HCI

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to se...

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Authors: Diaz Fortuny, Javier, Martin Martínez, Javier, Rodríguez Martínez, Rosana, Castro López, Rafael, Roca Moreno, Elisenda, Aragonès Cervera, Xavier|||0000-0003-1352-8675, Barajas Ojeda, Enrique|||0000-0002-2072-2268, Mateo Peña, Diego|||0000-0001-5996-9092, Fernández Fernández, Francisco V., Nafría Maqueda, Montserrat|||0000-0002-9549-2890
Format: article
Publication Date:2018
Country:España
Institution:Universitat Politècnica de Catalunya (UPC)
Repository:UPCommons. Portal del coneixement obert de la UPC
Language:English
OAI Identifier:oai:upcommons.upc.edu:2117/126049
Online Access:https://hdl.handle.net/2117/126049
https://dx.doi.org/10.1109/JSSC.2018.2881923
Access Level:Open access
Keyword:Integrated circuits
Aging
Bias temperature instability (BTI)
CMOS
Degradation
Hot carrier injection (HCI)
Negative BTI (NBTI)
Positive BTI (PBTI)
Random telegraph noise (RTN)
Reliability
Statistical characterization
Variability.
Circuits integrats
Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
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Summary:© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

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