Keeping control transfer instructions out of the pipeline in architectures without condition codes

This work was funded by the Ministry of Education CAICYT under contract Number 314-85

Detalhes bibliográficos
Autores:	Cortadella, Jordi\|\|\|0000-0001-8114-250X, Llaberia Griñó, José M.\|\|\|0000-0002-3753-4108, González Colás, Antonio María\|\|\|0000-0002-0009-0996
Formato:	informe técnico
Fecha de publicación:	1987
País:	España
Recursos:	Universitat Politècnica de Catalunya (UPC)
Repositorio:	UPCommons. Portal del coneixement obert de la UPC
Idioma:	inglés
OAI Identifier:	oai:upcommons.upc.edu:2117/110641
Acesso em linha:	https://hdl.handle.net/2117/110641
Access Level:	acceso abierto
Palavra-chave:	Computer architecture Branch instructions Pipelined processors Processadors segmentats Instruccions de salt Arquitectura d'ordinadors Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors

Descrição
Resumo:	This work was funded by the Ministry of Education CAICYT under contract Number 314-85