Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA
In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order t...
| Autores: | , , , , |
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| Tipo de recurso: | artículo |
| Fecha de publicación: | 2018 |
| País: | España |
| Institución: | Universidad Complutense de Madrid (UCM) |
| Repositorio: | Docta Complutense |
| Idioma: | inglés |
| OAI Identifier: | oai:docta.ucm.es:20.500.14352/11976 |
| Acceso en línea: | https://hdl.handle.net/20.500.14352/11976 |
| Access Level: | acceso abierto |
| Palabra clave: | Circuitos integrados Hardware Electrónica (Informática) 2203.07 Circuitos Integrados 2203 Electrónica |
| Sumario: | In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead. |
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