An architectural journey into RISC architectures for HPC workloads
The thesis evaluates the current state-of-the-art of RISC architectures in HPC. Studying the performance, power, and energy to solution in heterogeneous SoCs. For the evaluation 2 arm platforms (CPU+GPU, CPU+FPGA), 1 RISC-V platform and 1 Open Source RISC-V core running in an FPGA have been tested.
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2019 |
| País: | España |
| Institución: | Universitat Politècnica de Catalunya (UPC) |
| Repositorio: | UPCommons. Portal del coneixement obert de la UPC |
| Idioma: | inglés |
| OAI Identifier: | oai:upcommons.upc.edu:2117/131610 |
| Acceso en línea: | https://hdl.handle.net/2117/131610 |
| Access Level: | acceso abierto |
| Palabra clave: | Cluster High performance computing RISC-V FPGA OmpSs computació d'altes prestaciones clusterització programació heterogènia high-performance computing arm clustering heterogeneous programming Sistemes productius locals Càlcul intensiu (Informàtica) Àrees temàtiques de la UPC::Informàtica |
| Sumario: | The thesis evaluates the current state-of-the-art of RISC architectures in HPC. Studying the performance, power, and energy to solution in heterogeneous SoCs. For the evaluation 2 arm platforms (CPU+GPU, CPU+FPGA), 1 RISC-V platform and 1 Open Source RISC-V core running in an FPGA have been tested. |
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