Diseño de aceleradores hardware para procesado de audio en arquitecturas SoC
Real-time audio applications are demanding more computational cost day by day, due to the increase in complexity of the applications or due to the increase of audio channels to process. For that task, usually specific DSP architectures has been used (and still they are used), that are able to accomp...
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| Tipo de recurso: | tesis de maestría |
| Fecha de publicación: | 2016 |
| País: | España |
| Institución: | Universitat Politècnica de València (UPV) |
| Repositorio: | RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia |
| Idioma: | español |
| OAI Identifier: | oai:riunet.upv.es:10251/80440 |
| Acceso en línea: | https://riunet.upv.es/handle/10251/80440 |
| Access Level: | acceso abierto |
| Palabra clave: | digital signal processing digital filter codesign FPGA ARM audio SoC procesado digital de señal DSP filtro digital codiseño TECNOLOGIA ELECTRONICA Máster Universitario en Ingeniería de Telecomunicación-Màster Universitari en Enginyeria de Telecomunicació |
| Sumario: | Real-time audio applications are demanding more computational cost day by day, due to the increase in complexity of the applications or due to the increase of audio channels to process. For that task, usually specific DSP architectures has been used (and still they are used), that are able to accomplish most of the applications, but they get in struggle when the increase of computational cost is huge. To face this limitations there are several possibilities. One the one hand, increasing the number of DSP cores (actually up to 8 cores) with a ¿software¿ approach. On the other hand is the ¿hardware¿ approach using FPGAs architectures performing in the processing in parallel. This is the solution adopted by most of the actual digital mixers manufacturers, in combination with general purpose microprocessors for the user interface and control, due to the diversity on the actual FPGA market. DSP manufactures like Analog Devices have taken a mixed way, including in their DSP SHARC processors hardware accelerators for the most common audio algorithms like FFTs and FIR and IIR filters. Recently, the two major FPGA manufacturers (XILINK and ALTERA) have included in their portfolio mixed devices that include in the silicon FPGAs and 2 ARM Cortex-A9 general purpose processors. The objective of these new SoC is clear: split the designs in software (ARM) and hardware accelerators (FPGA) as advanced peripherals. They also want to attract software developers to the programmable devices. The proposed working flow for these devices made easy to move one software implemented part to hardware (even from C code), automatically solving all the drivers for configuring and using these new peripherals. This work wants to use these new mixed architectures, particularly using the Zynq from XILINX, in audio applications. The objective is to develop hardware accelerators on the FPGA of audio algorithms (filtering, mixing, dynamic range controllers, effects), with a theory study of the data word sizes (something very critic, mainly in low frequencies), use of noise-shaping structures and techniques, pipelining reuse of hardware resources, input-output, etc. |
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