Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codes

[EN] Belief propagation (BP) combined with ordered statistics decoding (OSD) provides a good balance between accuracy and complexity for many quantum error correction (QEC) codes, making it nearly universal. However, the complexity of OSD can limit real-time decoding, particularly for superconductin...

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Autores: Bascones, Daniel, Garcia-Herrero, Francisco, Valls Coquillat, Javier|||0000-0002-9390-5022
Formato: artículo
Fecha de publicación:2025
País:España
Recursos:Universitat Politècnica de València (UPV)
Repositorio:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
Idioma:inglés
OAI Identifier:oai:dnet:riunet______::fa264e2448cc15fb2d5e4ebda1fdbf24
Acesso em linha:https://riunet.upv.es/handle/10251/234049
Access Level:acceso abierto
Palavra-chave:Quantum error correction
Quantum LDPC codes
BP plus OSD
FPGA and ASIC decoders
Hardware emulation
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spelling Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codesBascones, DanielGarcia-Herrero, FranciscoValls Coquillat, Javier|||0000-0002-9390-5022Quantum error correctionQuantum LDPC codesBP plus OSDFPGA and ASIC decodersHardware emulation[EN] Belief propagation (BP) combined with ordered statistics decoding (OSD) provides a good balance between accuracy and complexity for many quantum error correction (QEC) codes, making it nearly universal. However, the complexity of OSD can limit real-time decoding, particularly for superconducting qubits, and the limits of classical hardware decoders have not been fully explored. Therefore, it is important to assess the architecture of OSD for different code families, such as surface codes and bicycle bivariate codes, under realistic assumptions like the detector error model. This paper introduces a BP + OSD parallel architecture implemented on FPGA and ASIC for surface codes (distances 3-21) and bicycle bivariate codes (distances 6-24). Results show that for surface codes up to distance 9, the OSD post-processor fits into a single VCU129 FPGA, achieving a frequency of 200 MHz with a worst-case latency of 134 mu s. For bicycle bivariate codes, the limit is distance 12, with a frequency of 244 MHz and a worst-case latency of 84 mu s. In ASIC, with 45 nm technology, latency improves by 31%, but area resources grow significantly, making parallel implementation beyond distance 12 impractical on a single chip. The designs were verified using a hardware emulator, ensuring that the decoder's behavior matches software simulations and revealing interesting results like potential error floors at low logical error rates.This work was supported by the project PID2023-147059OB-I00 funded by MCIU/AEI/10.13039/501100011033/FEDER, UE. F. Garcia-Herrero's work on this project was partially funded by a grant from Google Quantum AI. J. Valls work in this project was founded by European Union NextGenerationEU and Ministerio para la Transformacion Digital y de la Funcion Publica (Programa de Ayudas para la Creacion de Catedras Universidad-Empresa, grant TSI-069100-2023-0009).Departamento de Ingeniería ElectrónicaInstituto Universitario de Telecomunicación y Aplicaciones MultimediaEscuela Politécnica Superior de GandiaAgencia Estatal de InvestigaciónMinisterio de Asuntos Económicos y Transformación DigitalRepositorio Institucional de la Universitat Politècnica de València Riunet20252025-11-20journal articlehttp://purl.org/coar/resource_type/c_6501VoRhttp://purl.org/coar/version/c_970fb48d4fbd8a85info:eu-repo/semantics/articleapplication/pdfhttps://riunet.upv.es/handle/10251/234049reponame:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valénciainstname:Universitat Politècnica de València (UPV)InglésengAgencia Estatal de Investigación http://dx.doi.org/10.13039/501100011033 Plan Estatal de Investigación Científica y Técnica y de Innovación 2021-2023 PID2023-147059OB-I00 CORRECCION DE ERRORES EN SISTEMAS CUANTICOS: DEL ANALISIS DE ALGORITMOS A LA OPTIMIZACION DEL HARDWAREMINISTERIO DE ASUNTOS ECONOMICOS Y TRANSFORMACION DIGITAL MINISTERIO DE ASUNTOS ECONOMICOS Y TRANSFORMACION DIGITAL TSI-069100-2023-0009 Internacional UPV-VaSiC de Diseño Microelectrónico, hacia el Campus Internacional de Semiconductoresopen accesshttp://purl.org/coar/access_right/c_abf2Reconocimiento - No comercial - Sin obra derivada (by-nc-nd) http://creativecommons.org/licenses/by-nc-nd/4.0/info:eu-repo/semantics/openAccessoai:dnet:riunet______::fa264e2448cc15fb2d5e4ebda1fdbf242026-06-13T07:49:27Z
dc.title.none.fl_str_mv Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codes
title Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codes
spellingShingle Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codes
Bascones, Daniel
Quantum error correction
Quantum LDPC codes
BP plus OSD
FPGA and ASIC decoders
Hardware emulation
title_short Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codes
title_full Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codes
title_fullStr Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codes
title_full_unstemmed Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codes
title_sort Exploring the FPGA and ASIC design space of belief propagation and ordered statistics decoders for quantum error correction codes
dc.creator.none.fl_str_mv Bascones, Daniel
Garcia-Herrero, Francisco
Valls Coquillat, Javier|||0000-0002-9390-5022
author Bascones, Daniel
author_facet Bascones, Daniel
Garcia-Herrero, Francisco
Valls Coquillat, Javier|||0000-0002-9390-5022
author_role author
author2 Garcia-Herrero, Francisco
Valls Coquillat, Javier|||0000-0002-9390-5022
author2_role author
author
dc.contributor.none.fl_str_mv Departamento de Ingeniería Electrónica
Instituto Universitario de Telecomunicación y Aplicaciones Multimedia
Escuela Politécnica Superior de Gandia
Agencia Estatal de Investigación
Ministerio de Asuntos Económicos y Transformación Digital
Repositorio Institucional de la Universitat Politècnica de València Riunet
dc.subject.none.fl_str_mv Quantum error correction
Quantum LDPC codes
BP plus OSD
FPGA and ASIC decoders
Hardware emulation
topic Quantum error correction
Quantum LDPC codes
BP plus OSD
FPGA and ASIC decoders
Hardware emulation
description [EN] Belief propagation (BP) combined with ordered statistics decoding (OSD) provides a good balance between accuracy and complexity for many quantum error correction (QEC) codes, making it nearly universal. However, the complexity of OSD can limit real-time decoding, particularly for superconducting qubits, and the limits of classical hardware decoders have not been fully explored. Therefore, it is important to assess the architecture of OSD for different code families, such as surface codes and bicycle bivariate codes, under realistic assumptions like the detector error model. This paper introduces a BP + OSD parallel architecture implemented on FPGA and ASIC for surface codes (distances 3-21) and bicycle bivariate codes (distances 6-24). Results show that for surface codes up to distance 9, the OSD post-processor fits into a single VCU129 FPGA, achieving a frequency of 200 MHz with a worst-case latency of 134 mu s. For bicycle bivariate codes, the limit is distance 12, with a frequency of 244 MHz and a worst-case latency of 84 mu s. In ASIC, with 45 nm technology, latency improves by 31%, but area resources grow significantly, making parallel implementation beyond distance 12 impractical on a single chip. The designs were verified using a hardware emulator, ensuring that the decoder's behavior matches software simulations and revealing interesting results like potential error floors at low logical error rates.
publishDate 2025
dc.date.none.fl_str_mv 2025
2025-11-20
dc.type.none.fl_str_mv journal article
http://purl.org/coar/resource_type/c_6501
VoR
http://purl.org/coar/version/c_970fb48d4fbd8a85
dc.type.openaire.fl_str_mv info:eu-repo/semantics/article
format article
dc.identifier.none.fl_str_mv https://riunet.upv.es/handle/10251/234049
url https://riunet.upv.es/handle/10251/234049
dc.language.none.fl_str_mv Inglés
eng
language_invalid_str_mv Inglés
language eng
dc.relation.none.fl_str_mv Agencia Estatal de Investigación http://dx.doi.org/10.13039/501100011033 Plan Estatal de Investigación Científica y Técnica y de Innovación 2021-2023 PID2023-147059OB-I00 CORRECCION DE ERRORES EN SISTEMAS CUANTICOS: DEL ANALISIS DE ALGORITMOS A LA OPTIMIZACION DEL HARDWARE
MINISTERIO DE ASUNTOS ECONOMICOS Y TRANSFORMACION DIGITAL MINISTERIO DE ASUNTOS ECONOMICOS Y TRANSFORMACION DIGITAL TSI-069100-2023-0009 Internacional UPV-VaSiC de Diseño Microelectrónico, hacia el Campus Internacional de Semiconductores
dc.rights.none.fl_str_mv open access
http://purl.org/coar/access_right/c_abf2
Reconocimiento - No comercial - Sin obra derivada (by-nc-nd)
http://creativecommons.org/licenses/by-nc-nd/4.0/
dc.rights.openaire.fl_str_mv info:eu-repo/semantics/openAccess
rights_invalid_str_mv open access
http://purl.org/coar/access_right/c_abf2
Reconocimiento - No comercial - Sin obra derivada (by-nc-nd)
http://creativecommons.org/licenses/by-nc-nd/4.0/
eu_rights_str_mv openAccess
dc.format.none.fl_str_mv application/pdf
dc.source.none.fl_str_mv reponame:RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname:Universitat Politècnica de València (UPV)
instname_str Universitat Politècnica de València (UPV)
reponame_str RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
collection RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
repository.name.fl_str_mv
repository.mail.fl_str_mv
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score 15.228081

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