Exploring Low-Cost Platforms for Automatic Chess Digitization

Automatic digitization of chess games through computer vision poses a considerable technological challenge. This capability holds significant appeal for tournament organizers and both amateur and professional players, enabling them to broadcast over-the-board (OTB) games online or facilitate in-dept...

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Bibliographic Details
Authors: Mallasén Quintana, David, Belda Beneyto, Maria José, Del Barrio García, Alberto Antonio, Castro Rodríguez, Fernando, Olcoz Herrero, Katzalin, Prieto Matías, Manuel
Format: article
Publication Date:2025
Country:España
Institution:Universidad Complutense de Madrid (UCM)
Repository:Docta Complutense
Language:English
OAI Identifier:oai:docta.ucm.es:20.500.14352/125900
Online Access:https://hdl.handle.net/20.500.14352/125900
Access Level:Open access
Keyword:Acceleration
Chess pieces classification
Computer vision
Neural networks
RISC-V
Hardware
3304.06 Arquitectura de Ordenadores
Description
Summary:Automatic digitization of chess games through computer vision poses a considerable technological challenge. This capability holds significant appeal for tournament organizers and both amateur and professional players, enabling them to broadcast over-the-board (OTB) games online or facilitate in-depth analysis with chess engines. While existing research provides encouraging results, there’s an ongoing demand to enhance recognition accuracy and minimize processing delays, particularly when leveraging affordable hardware. In our study, we adapted these techniques specifically for cost-effective single-board computers like the Nvidia Jetson Nano. Our framework combines a swift chessboard detection method with a Convolutional Neural Network for piece recognition. Notably, it can interpret an image of a chessboard setup in under a second, achieving accuracies of 92% in piece identification and 95% in board detection. Furthermore, we assessed a custom open-hardware platform equipped with affordable, low-power RISC-V processors. On their own, these processors were inadequate for realtime tasks. However, when paired with a systolic array accelerator, their performance significantly improved, yielding promising results in both piece classification and board detection.