COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
The growing trend of pervasive computing has consolidated the everlasting need for power efficient devices. The conventional cache subsystem of general-purpose CPUs, while being able to adapt to many use cases, suffers from energy inefficiencies in some scenarios. It is well-known by now in the acad...
| Authors: | , , , |
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| Format: | article |
| Publication Date: | 2023 |
| Country: | España |
| Institution: | Universidad Complutense de Madrid (UCM) |
| Repository: | Docta Complutense |
| Language: | English |
| OAI Identifier: | oai:docta.ucm.es:20.500.14352/88544 |
| Online Access: | https://hdl.handle.net/20.500.14352/88544 |
| Access Level: | Open access |
| Keyword: | Cache Compaction Energy efficiency Data reuse Scratchpad Informática (Informática) 1203.17 Informática |
| Summary: | The growing trend of pervasive computing has consolidated the everlasting need for power efficient devices. The conventional cache subsystem of general-purpose CPUs, while being able to adapt to many use cases, suffers from energy inefficiencies in some scenarios. It is well-known by now in the academic literature that the utilization of a scratchpad memory (SPM) can help reducing the overall energy consumption of embedded systems. This work proposes a hybrid cache-SPM architecture with support logic for semi-transparent data management and spatial locality improvement. Selected data are transferred and stored in the SPM in a compact form using dynamic layout transformation. As a second major contribution, we introduce a methodology to identify memory access sequences that make an inefficient use of the cache, marking them as candidates to be moved to an SPM of constrained space. The methodology does not require access to the source code of the target applications, relying on binary instrumentation and offline profiling. The resulting mapping policies have been tested on a simulated system, showing a mean memory dynamic energy reduction of 43% and a mean speed gain of 13% with a representative benchmark set. |
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